CDPD系统Reed-Solomon编解码芯片低复杂度实现  

VLSI Implementation of A Reed-Solom on Encoder and Decoder For the Communication

作　　者：葛群[1] 毛军发[1] 戎蒙恬[1] 

机构地区：[1]上海交通大学

出　　处：《微电子学与计算机》2002年第3期24-27,共4页Microelectronics & Computer

摘　　要：本文给出了一个面积优化、低复杂度、具有8位纠错能力的Reed-Solomon(63,47)编解码芯片的VLSI实现。此芯片将用于CDPD(CellularDigitalPacketData)通信系统犤1犦。由于Euclid算法规则、简单,很自然地适合VLSI实现,因此本文采用Euclid算法实现RS解码部分。在编码部分里,又采用了基于特定复合域的常数乘法器,它极大的降低了编码器的面积。同时基于复合域GF((2n)2)的乘法器的采用极大地降低了RS解码器的乘法复杂度。此RS编解码芯片能独立的工作在15MHz。芯片采用0.6um1P2MCMOS5v电压的工艺进行制造。芯片最终裸片面积是4mmx4mm。芯片成功经过测试并满足CDPD通讯系统的要求。This paper presents VLSI implementa tion of an area efficient 8-error correcting(63,47)Reed -Solomon(RS)en-code r and decoder for the CDPD(Cellular Digital Packet Data)communication systems .We implement this RS decoder using Euclidean algorithms which is regul a r,simple and naturally suitable for VLSI implementation.C onstant multipliers based on certain composite field are deploye d in the encoder,which sig-nifica ntly decreases the encoder' s area.Multipliers over certain composite field GF ((2n)2)adopted in this paper lowers the complexity of the multiplicati on of the d ecoder.The RS encoder and decoder can independently opera tes at a clock freque ncy of30MHz.This chip was fabricated in 0.6um CMOS 1P2M tech-nology wit h a supply of voltage of 5v,with die area 4mm x 4mm.The chip has been fully tested and str atifies the demand of the CDPD communication systems.

关 键 词：CDPD系统 Reed-Solomon编解码芯片 低复杂度 蜂窝移动电话网 

分 类 号：TN929.53[电子电信—通信与信息系统] TN762[电子电信—信息与通信工程]