基于PC总线控制的带锁相环的多路数据采集卡的设计  

Design of multiplex data sampling card with phase-locked loop based on PC-bus

作　　者：吴炳超[1] 刘会金[1] 王茂海[1] 

机构地区：[1]武汉大学电气工程学院,武汉430072

出　　处：《电测与仪表》2002年第5期47-50,10,共5页Electrical Measurement & Instrumentation

摘　　要：根据抽样频率为信号频率的整数倍,抽样点数包括整周期,且满足抽样定理时,用DFT做频谱分析,频域不会发生泄漏,可完全消除误差的理论,介绍了采用简单可靠和快速的硬件锁相实现同步采样的原理,以及基于PC总线实现同步采样数据采集系统的设计。This paper introduces the principle of synchronous sampling accomplished by phase locking with simple and reliable and fast hardware and the design of synchronous sampling date-collect system, which is based on the theory that when sampling frequency is the integer times of signal frequency and integer period is sampled. In according to sampling theory and analyzed by DFT, the spectral leakage will not occur in frequency domain and error can be eliminated completely.

关 键 词：多路数据采集卡 设计 锁相环 分频器 同步采样 PC总线 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]