用FPGA实现RS-485通信接口芯片  

RS-485 Communication Interface Chip With FPGA

作　　者：梁士龙[1] 王力男 杨嘉伟[3] 

机构地区：[1]中国航天科工集团公司二院25所,北京100854 [2]信息产业部电子54所,河北石家庄050081 [3]中国航天科工集团公司研发中心,北京100830

出　　处：《系统工程与电子技术》2002年第4期103-106,共4页Systems Engineering and Electronics

摘　　要：在点对多点主从通信系统中 ,需要合适的接口形式和通信协议实现主站与各从站的信息交换。RS -4 85接口是适合这种需求的一种标准接口形式。当选择主从多点同步通信方式时 ,工作过程与帧格式符合HDLC/SDLC协议。介绍了采用VHDL语言在FPGA上实现的以HDLC/SDLC协议控制为基础的RS - 4 85通信接口芯片。实验表明 ,这种接口芯片操作简单、体积小、功耗低、可靠性高 ,极具实用价值。In a master slave point to multipoint communication system, appropriate interface type and communication protocol are needed to realizd the information exchange between the master node and slave nodes. RS 485 interface is one of such standard interfaces satisfying this demand. When the master slave multipoint synchronous communication mode is chasen, the operation and frame format comply with HDLC/SDLC protocol. In this paper, an RS 485 communication interface chip based on HDLC/SDLC protocol is introduced, which is implemented in a single chip FPGA with VHDL language. The application result shows that the interface chip is of practical use because it has the characteristics of easy operation, small volume, low power consumption and high reliability.

关 键 词：FPGA RS-485通信接口芯片 通信系统 标准接口 芯片 

分 类 号：TN492[电子电信—微电子学与固体电子学] TP334.7[自动化与计算机技术—计算机系统结构]