小面积低功耗掩膜ROMASIC设计  

A Small Area Low Power Consumption Mask ROM ASIC Design

作　　者：崔嵬[1] 韩月秋 陈禾[1] 李昀 

机构地区：[1]北京理工大学电子工程系,北京100081

出　　处：《电子学报》2002年第6期934-936,共3页Acta Electronica Sinica

基　　金：国防科技预研基金 (No .99J.1 .4.8.BQ0 1 0 8)

摘　　要：本文介绍了一种利用 0 6 μm单硅双铝双阱CMOS工艺实现的 4Kbit掩膜ROM专用集成电路设计 (A SIC) .ROM单元应用串行结构 ,整个芯片的面积为 0 0 82mm2 .在 5伏电源下 ,功率延迟积为 0 0 36PJ/bit,最大工作电流为 1 2mA ,最大静态漏电流为 0 1μA .采用一种新颖的灵敏放大器有效地提高了ROM的访问速度 ,ROM的访问时间为36ns.The ASIC design of a 4K bit mask-programmable CMOS ROM is introduced,and the ROM has a small area of 0 082mm 2 with a power-delay product of 0 036PJ/bit.The high packing density and the excellent power-delay product have been achieved by using double well,single polysilicon,double metal 0 6μm CMOS technology and a serial ROM cell structure.The power supply currents in active and quiescent modes are 1 2mA and less than 0 1μA at +5V,respectively.Using a novel and simple sensitive amplifier/driver structure efficiently reduces the memory access time.The memory access time is 36ns.

关 键 词：掩膜ROM ASIC设计 CMOS工艺 只读存贮器 ROM 低功耗 译码器 灵敏放大器 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]