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出 处:《半导体技术》2014年第7期532-538,553,共8页Semiconductor Technology
基 金:国家科技重大专项资助项目(2011ZX02501)
摘 要:研究了40 nm工艺中低阻值接触栓的电迁移性能的提升。高性能芯片要求接触栓电阻尽可能小,而接触栓尺寸的减小使低电阻率钨成为必然选择。新材料的引入和尺寸减小等因素使传统工艺中较为稳定的接触栓的电迁移可靠性面临新的挑战。通过减少电化学腐蚀、改善金属填充、强化界面结合力及减少应力失配等,形成综合性解决方案。最终封装级电迁移可靠性测试结果为:激活能Ea为0.92 eV,电流密度指数n为1.12,寿命为86.3年(超过10年的标准)。与最初工艺相比,消除了顶部腐蚀和中心空隙的缺陷形貌,接触栓电阻优于设计标准,抗电迁移寿命提高超过一千万倍,极大地提高了接触栓的电迁移性能。The improvement of the electron-migration for the low resistance contact in 40 nm node was researched. Higher chip performance requires lower contact resistance. With the contact size shrinking,low resistance tungsten becomes an inevitable choice. New material introducing,pattern shrinking and other factors make the electron-migration reliability of the contact which is stable in the traditional process face new challenges. Systematical solutions were proposed by lessening the electrochemical corrosion,improving the metal filling,enhancing the interface adhesion and reducing the stress mismatch. Finally,the package electron-migration reliability test result shows that Eais0. 92 eV,n is 1. 12 and the life time is 86. 3 years( longer than the target of 10 years). Compared with the initial process,the seam and erosion were eliminated and the contact resistance was lower than the target. A stable and qualified process was acquired with the electron-migration resistance life time 107times longer,thus the electron-migration of the contact was greatly improved.
关 键 词:电迁移可靠性 低电阻率 钨 化学腐蚀 界面结合力 应力失配
分 类 号:TN306[电子电信—物理电子学]
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