一种基于连续页面归并回收的旁路转换缓冲器  

Translation look-aside buffer with consecutive page merging and recycling

作　　者：杨婷[1] 郝子轶[1] 李春强[1] 孟建熠[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,杭州310027

出　　处：《计算机应用研究》2014年第8期2376-2379,共4页Application Research of Computers

摘　　要：旁路转换缓冲器(TLB)是内存管理单元中加速虚拟页号到物理页号转换过程的核心部件。基于程序连续页面分配访问的局部性特征,提出一种基于连续页面归并回收的TLB地址映射框架。在基于两路组相联结构的Main TLB基础上,设计一个用于合并回收页面的RTLB,当Main TLB由于地址映射块冲突发生替换时,检查Main TLB中是否存在与旧翻译信息的虚拟页号(VPN)、物理页号(PPN)都连续的表项,并临时缓存到RTLB进行连续页面归并,合并后的表项映射范围扩大,有效提高了TLB的映射效率。基于EEMBC测试基准的实验表明,在表项数相同的情况下,提出的TLB与传统TLB相比,缺失率降低了47.72%,平均访问时间降低了4.42%,具有高性能、低功耗的特点。Translation look-aside buffer（ TLB） is the essential component of memory management unit for accelerating the translation from virtual page number（ VPN） to physical page number（ PPN）. Based on the locality of reference in continuous page allocation and accessing,this paper proposed a 2-stage TLB architecture with consecutive page merging and recycling. By using RTLB for page merging and recycling,when old translation information in Main TLB was to be covered because of conflict,this TLB architecture would check whether the consecutive page of old entry was in Main TLB,then merged them and recycled into RTLB which could be reused later. The merged entry in RTLB with expanded mapping range could improve the mapping efficiency significantly. Experimental results from EEMBC show that the miss ratio of the proposed TLB decreases by47. 72% and the average access time decreases by 4. 42% compared to TLB architecture with the same entries in MTLB,which supports high performance and low cost embedded application.

关 键 词：内存管理单元 旁路转换缓冲器 连续页面归并 页面回收 低功耗 高性能 

分 类 号：TP303[自动化与计算机技术—计算机系统结构] TN47[自动化与计算机技术—计算机科学与技术]