基于高性能浮点乘累加器的浮点协处理器设计  

Design of high performance FP unit in coprocessor

作　　者：邹翠[1] 谢憬[1] 谢鑫君 

机构地区：[1]上海交通大学微电子学院,上海200240 [2]上海通用识别技术研究所,上海201112

出　　处：《信息技术》2014年第7期121-124,共4页Information Technology

摘　　要：复杂运算中经常需要处理取值范围大、精度高的浮点型数据,一般的低端嵌入式内核中没有浮点硬件单元,采用软件模拟浮点运算往往不能满足实时性要求。现研究基于高性能浮点乘累加的通用浮点协处理器设计与实现,重点研究提升浮点运算能力、减少硬件开销等关键技术。实验结果显示向量浮点协处理器运算周期减少40%以上。Processing of wide range and high precision FP data are necessary, m many cornplexltycalculates. But embedded developers often experience the condition of having no hardware float point unitin their low-power system. Software simulation of float-point calculation may not meet the real-time need.The article presents the FP coprocessor based on a high performance FP multiply accumulate unit. Mainaim of this work is to propose a lightweight structure, capable of perform efficiendy FP operations withlow dynamic power. The test result shows a 40 percentage decrease of calculating cycles.

关 键 词：浮点运算 浮点乘累加(FPMAC) 批量运算 浮点协处理器 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构]