面向FPGA的低功耗多路选择器设计方法  

Design of low-power multiplexers for FPGA

作　　者：李列文[1,2] 桂卫华[1] 阳春华[1] 胡小龙[1] 

机构地区：[1]中南大学信息科学与工程学院,湖南长沙410075 [2]长沙师范学院电子信息工程系,湖南长沙410100

出　　处：《中南大学学报（自然科学版）》2014年第5期1496-1502,共7页Journal of Central South University:Science and Technology

基　　金：国家自然科学基金重点资助项目(61134006)

摘　　要：针对现场可编程门阵列(FPGA)因集成度与速度提高引起的功耗问题,提出一种适合于FPGA的低功耗多路选择器设计方法。该方法基于FPGA中被使用的多路选择器内存在大量闲置晶体管这一现象,采用反向衬底偏置技术对被使用多路选择器中闲置晶体管的泄漏电流进行优化。仿真结果表明:与传统结构多路选择器相比,在保证其他性能的前提下,采用该方法设计的多路选择器泄漏功耗可降低约28.97%。此外,该方法也可应用于FPGA中未被使用多路选择器泄漏电流的优化,可以进一步大幅度降低FPGA的静态功耗。Aiming at the increasingly serious power dissipation problem of field programmable gate array （FPGA） caused by their growing integration and speed, a new design method for multiplexers suitable for FPGA was proposed. Based on the phenomenon of the used multiplexers in FPGA containing many idle transistors, the proposed method reduces the leakage power dissipation of idle transistors in multiplexer by using reverse body bias technique. The simulation results show that the leakage power of multiplexers designed with the new method can be reduced by about 28.97% of that of conventionally designed multiplexers while maintaining other performance. In addition, the proposed method can reduce the leakage power dissipation of unused multiplexers in FPGA and further sharply reduce the static power of FPGA.

关 键 词：低功耗 多路选择器 反向衬底偏置技术 现场可编程门阵列 

分 类 号：TN402[电子电信—微电子学与固体电子学]