LDPC与Turbo解码器中的专用控制器设计  

Design of Application Specific Control Processor for LDPC and Turbo Decoder

作　　者：黄睿[1] 杨庆庆[1] 程洁琼[1] 周晓方[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海200433

出　　处：《计算机工程》2014年第7期1-6,共6页Computer Engineering

基　　金：国家科技重大专项基金资助项目(2011ZX03003-003-03);专用集成电路与系统国家重点实验室基金资助项目(11MS003)

摘　　要：对于兼容LDPC和Turbo码的多模通信信道解码器,解码过程涉及大量数据计算和传输,系统高吞吐率的实时性要求使这类多模解码器的结构变得日益复杂。为此,设计并实现一种专用控制器,对待解码数据进行预处理,以控制整个解码器系统的工作。为满足解码器系统高时钟频率、大量专用运算和数据快速传输3个要求,采用重划分控制器流水线、增加专用指令及加速器和片内存储器划分3种方法,使解码器系统最大程度地实现并行化计算处理。测试结果表明,在专用控制器的控制协调下,解码器能满足LTE标准1 Gb/s和UMTS标准672 Mb/s的高吞吐率要求。使用TSMC 65 nm低功耗库,通过后端布局进行布线设计后,该解码器面积约为490 000μm2,最大时钟频率为540MHz。There are a lot of calculations and data transmitting in the flexible Low Density Parity Check（LDPC） code and Turbo channel decoder. In order to meet the high throughput requirement, the decoder becomes more and more complicated. To solve this problem, an Application Specific Control Processor（ASCP） is proposed which pre-calculates the encoded data and controls the work of the whole decoder system. This high output decoder has three requirements for the control processor： high clock frequency, massive specific calculations and massive data transmitting. By designing the processor＇s pipeline, application specific instruction sets, accelerators and memory structure, the decoder can run at a high paralleled status. As a result, the decoder can meet the high throughput requirement of LTE standard 1 Gb/s and UMTS standard 672 Mb/s. The placement and routing result is 490 000μm2 with clock frequency 540 MHz using TSMC 65 nm low power lib and backend layout wiring.

关 键 词：专用控制器 解码器 流水线划分 加速器 存储器划分 LDPC码 TURBO码 

分 类 号：TN492[电子电信—微电子学与固体电子学]