可重构浮点混合/连续乘-加器的设计与实现  

Design and Implementation of Reconfigurable Floating-point Fused/Continuous Multiply-adder

作　　者：洪琪[1] 何敏[1] 范继聪 袁粲 

机构地区：[1]安徽大学电子信息工程学院,合肥230601

出　　处：《计算机工程》2014年第7期272-276,共5页Computer Engineering

基　　金：国家"863"计划基金资助项目(2009AA012201);专用集成电路与系统国家重点实验室开放基金资助项目(12KF004)

摘　　要：浮点连续乘-加、混合乘-加和三操作数加等浮点算术运算在科学计算领域中应用越来越频繁,为设计一款支持浮点连续乘-加、混合乘-加和三操作数加的多功能浮点运算单元,提出一种可重构浮点混合/连续乘-加器,通过对控制位的配置可以实现多种浮点数据操作。该乘-加器采用8级流水线,可以实现单周期的浮点乘累加,大幅提高数据处理吞吐量,同时支持三操作数加和两操作数和的累加。在Modelsim SE6.6f中对该设计进行仿真验证,结果表明其能够在Xilinx Virtex-6 FPGA上实现,资源消耗2 631个LUT,频率可达250 MHz,结果证明该浮点混合/连续乘-加器具有较大的使用价值。As floating-point continuous multiply-add, fused multiply-add and multiply and three-operands addition operations are used more and more frequently in the field of scientific computing, a multi-purpose floating-point unit is designed which supports floating-point continuous multiply-add, fused multiply-add and multiply and three-operands addition is an urgent need. In this situation, a reconfigurable floating-point fused/continuous multiply-add structure is proposed. This reconfigurable floating-point fused/continuous multiply-adder can achieve a variety of floating-point data manipulation through configuration of the control bit. This reconfigurable floating-point fused/continuous multiply-adder uses eight-stage pipe-line. It can achieve single-cycle multiply-accumulate, which greatly improves the throughput of the data processing and supports three-operand addition and two-operand sum’s accumulate simultaneously. This design is simulated and verified in Modelsim SE6.6f’s environment and the function is correct. When this design is implemented on Xilinx Virtex-6 FPGA, the resource consumption is 2 631 LUTs and the frequency is up to 250 MHz, and the result proves that the reconfigurable floating-point fused/continuous multiply-adder has a large value in use.

关 键 词：浮点 连续乘-加 混合乘-加 三操作数加 可重构 流水线 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]