数字IO电路板的嵌入式测试性设计方案  

Embedded DFT Solution of Digital IO Circuit Board

作　　者：杜影[1] 吴朝华[1] 李洋[1] 徐鹏程[1] 

机构地区：[1]北京航天测控技术有限公司,北京100041

出　　处：《计算机测量与控制》2014年第7期2027-2030,共4页Computer Measurement &Control

基　　金：总装备部预研项目(51317040204)

摘　　要：近年来,随着DSP、FPGA等大规模集成电路的发展,电子系统的性能也在大大提高,但同时给电子系统带来了新的测试和故障诊断问题;为了解决电路板快速诊断维修问题,嵌入式测试正以全新的概念成为板级电路测试的研究方向;文中从嵌入式测试的基本概念出发,介绍了嵌入式边界扫描、非侵入式测试等先进的板级嵌入式测试技术,并阐述了模拟嵌入式测试性设计的难点和基础电路原则,同时给出了基于FPGA的嵌入式测试控制器设计方案;然后,面向数字IO电路板,针对其关键功能电路展开嵌入式测试性设计,简要说明了测试程序的开发与下载;根据测试验证结果,嵌入式测试性设计可以增强测试自动化、提高测试效率,从而能够更好地降低产品整个寿命周期的测试维修成本。In recent years, with the development of DSP, FPGA and other VLSI, the performance of electronic systems is greatly increasing. However, they also brought a new problem of testing and fault diagnosis at the same time. For solving the problem of fast diagnosis and maintenance on circuit board, the embedded test has becoming a research topics. Based on it, the embedded boundary-scan technology and the non-incursive board test technology are introduced firstly. Then the difficulty of the analog BIST （built-in self test） and its fundamental principle are illustrated. And an embedded controller solution based on FPGA is given. The embedded DFT targeted at the key function circuits of the digital IO board is presented, the test program development and download are described in brief. Based on the prepared test results, the embedded DFT is used to further enhance the test automation and the test efficiency. It can decrease the life cycle cost of test and maintenance greatly.

关 键 词：嵌入式测试 可测性 边界扫描 BIST 

分 类 号：TP3[自动化与计算机技术—计算机科学与技术]