利用PowerPC对多片FPGA并行配置的设计与实现  

Design and realization of parallel configuration of multiple FPGAs based on PowerPC

作　　者：赵陆文[1] 缪志敏[2] 张北江[1] 刘波[1] 

机构地区：[1]解放军理工大学通信工程学院,江苏南京210007 [2]解放军理工大学指挥信息系统学院,江苏南京210007

出　　处：《电子技术应用》2014年第8期17-19,23,共4页Application of Electronic Technique

基　　金：北斗二号卫星导航国家科技重大专项项目;中国博士后科学基金

摘　　要：为了克服JTAG等常用FPGA配置方式存在的下载速度慢等缺点,设计了一种利用PowerPC对多片FPGA进行并行配置的方案。借助PowerPC通用输入/输出口产生控制逻辑,利用其本地总线并行下载配置数据。该方案可以选择8 bit、16 bit以及32 bit位宽下载方式,依次实现对多片FPGA的并行配置。经实测,利用JTAG口对XC6VSX475T芯片进行配置需要48 s,而采用本方案可将配置时间缩短至1 s左右,大大缩短了配置时间。In order to overeome the shortages of common configuration modes, such as slowly speed, a parallel configuration scheme is put forward. Multiple FPGAs can be parallelly configured by PowerPC. The control logic, is produced by PowerPC＇s GPI- O, and the configuration data is downloaded through PowerPC＇s Local Bus. There are three bus width modes can be chosen, 8 bit, 16 bit and 32 bit. The test results show that it requires 48 seconds configuration XC6VSX475T using JTAG mode, however, the time can be shortened to about 1 second using the proposed scheme.

关 键 词：POWERPC FPGA 并行配置 

分 类 号：TN391[电子电信—物理电子学]