基于FPGA的实时视频缩放算法设计实现  

Design and implementation of real-time video scaling algorithm based on FPGA

作　　者：杨大伟[1,2] 李健[1] 

机构地区：[1]哈尔滨工程大学信息与通信工程学院,黑龙江哈尔滨150001 [2]大连民族学院机电信息与工程学院,辽宁大连116600

出　　处：《电子技术应用》2014年第8期34-37,共4页Application of Electronic Technique

基　　金：黑龙江省科技攻关项目(GC12A305)

摘　　要：通过权衡几种线性插值算法的显示效果和硬件可实现性,选择用双线性插值算法实现视频缩放,并在FPGA平台上以RAM_FIFO架构作为该算法硬件实现的核心思想,设计主要包括数据缓存模块、系数产生模块以及整体控制模块。结果表明,该设计能够实现任意比例缩放,系统频率高,实时性好,缩放后显示清晰稳定,能够满足实际工程的应用要求。Through analyzing the trading off display effect and hardware realizability of several linear interpolation algorithms, the paper selects to implement video scaling by bilinear interpolation algorithm and uses RAM_FIFO architecture as the heart of algorithms implementation based on FPGA. The design mainly consists of the data buffer module, the coefficient generation module and the whole control module. The result indicates that the system can realize arbitrary scaling,and its flexibility, real-time and display effect are good, which can meet the application requirements of the actual project.

关 键 词：视频缩放 FPGA 双线性插值 RAM_FIFO 

分 类 号：TN911.73[电子电信—通信与信息系统]