基于CPLD的FPGA从并快速加载方案  

Fast Serial Parallel Loading Scheme of FPGA Basing on CPLD

作　　者：李春雨[1] 

机构地区：[1]浙江机电职业技术学院电气电子工程学院,浙江杭州310053

出　　处：《中兴通讯技术》2014年第4期57-59,共3页ZTE Technology Journal

基　　金：基于X86嵌入式处理器在线侦错卡的开发(A-0271-14-029)

摘　　要：提出了基于复杂可编程逻辑器件(CPLD)的现场可编程门阵列(FPGA)从并加载方案,及逻辑代码的实现过程,并给出仿真结果。该方案理论计算结果表明,当加载SPARTAN-6系列最高端的6SLX150T时,采用基于CPLD的从并加载方式,共需要加载时间为1.221 s,完全满足通信产品的快启动要求,具有较高的应用价值。This paper describes field programmable gate array （FPGA） parallel loading scheme, which is based on complex programmable logic device （CPLD）. This paper also describes the implementation process of logic code and provides simulation results. The calculation results of this scheme show that using a CPLD-based parallel-loading scheme when loading the 6SLX150T （highest level of SPARTAN-6）, the loading time is just 1.221 s. This fully satisfies the quick boot of communication products and has higher application value.

关 键 词：FPGA CPLD 控制器 从并 加载 启动 

分 类 号：TN791[电子电信—电路与系统]