用于导航解算的矩阵运算硬件加速器设计  

Design of Matrix Computation Hardware Accelerator Applied in Navigation Calculation

作　　者：马邺晨[1] 李醒飞[1] 

机构地区：[1]天津大学精密测试技术及仪器国家重点实验室,天津300072

出　　处：《计算机工程》2014年第8期259-263,共5页Computer Engineering

基　　金：精密测试技术及仪器国家重点实验室开放基金资助项目(pil1006)

摘　　要：针对捷联式惯导系统中浮点矩阵乘积计算量大、串行处理方法耗时多制约捷联式惯导系统实时性提升的问题,提出一种基于FPGA/SOPC的浮点矩阵乘积并行处理方法。该处理方法的核心——高性能矩阵乘积单元是在脉动阵列结构基础上通过循环分块、数据空间分割及迭代空间合并优化后的高并行度处理单元,并利用直接内存存取大批量数据传输的速度优势,运算速度得到进一步提升。实验结果表明,据此设计的浮点矩阵乘积加速器不但能够准确地完成运算,而且运算速率有明显提升,较其他串、并行计算方法消耗的周期数分别减少71.3%,78%以上,能够有效地提高导航系统的实时性。In Strap-down Inertial Navigation System （SINS）,the floating-point matrix multiplication is complicated and time-consuming,especially in serial way.Therefor the calculation is a constraint of developing SINS＇ s real-time.To solve the problem,a sort of method in parallel based on FPGA/SOPC （System on a Programmable Chip） is put forward.The core of this method is the high-performance matrix multiplication cell whose structure is formed on systolic array basis with optimizing by loop tiling,data space diving and iteration space combining.Together with the remarkable speed advantage of Direct Memory Access （DMA） for mass data exchange,the operating rate of matrix multiplication is boosted further.The accelerator relied on the principle mentioned above is worked out.The result of test illustrates that the accelerator has ability to carry out the specific computation accurately and fast,and its speed performance is especially prominent.The cycles that accelerator consumed is decreased by above 71.3％,78％ compared with serial and its counterpart method.In conclusion,the accelerator provides a new idea for enhancing navigation systems＇ real-time.

关 键 词：捷联式惯导系统 浮点矩阵乘积运算 浮点宏功能模块 直接内存存取 加速器 

分 类 号：TP273[自动化与计算机技术—检测技术与自动化装置]