基于FPGA的祖冲之算法硬件实现  

Hardware Implementation of ZUC Algorithm Based on FPGA

作　　者：郭泓键[1,2] 董秀则[2] 高献伟[1,2] 

机构地区：[1]西安电子科技大学通信工程学院,西安710071 [2]北京电子科技学院,北京100070

出　　处：《计算机工程》2014年第8期268-272,共5页Computer Engineering

基　　金：北京市教育教号改革基金资助项目(121);北京电子科技学院教研基金资助项目(JY201218)

摘　　要：为在现场可编程门阵列(FPGA)平台上更高效地实现祖冲之算法,提出一种新的硬件实现方法。利用祖冲之算法的迭代特性、并行特性以及模加的性质,减少加法器的使用数量,包括使用资源占用少、延时少的简单加法器替代资源占用多、延时长的进位保留加法器以及mod(231-1)加法器,实现祖冲之算法关键路径中多次mod(231-1)加法运算。使用QuartusⅡ与ISE软件进行了仿真验证,结果表明,该方法在芯片资源占用仅为305个slice的情况下达到了5.322 Gb/s的吞吐量,与目前已有的最优实现方法相比,芯片资源占用减少了近23%,单位面积的吞吐量提高了25.9%,可以在减少芯片硬件资源占用的同时快速实现ZUC算法。In order to implement ZUC algorithm more efficiently on Field Programmable Gate Array （FPGA） platform,this paper comes up with a new method.This method utilizes the iterative nature and parallel feature of ZUC algorithm and utilizes the property of modular addition,reduces the number of adders,including substitutes simple adder which has less hardware resources and less hardware delay for carry save adder and mod（231-1） adder which have more hardware resources and more hardware delay.In this way,it implements the mod （231-1） additions in the critical path of ZUC algorithm,simulates and tests the method on Quartus Ⅱ and ISE,campares the simulate results with other known methods and present analysis.Expermental results show that this method can reach 5.322 Gb/s throughput with only 305 slices in hardware resources employment.Compared with the best published method,the method gives some 23％ decrement in hardware resources employment and 25.9％ increasement in throughput per unit area,and it can implement ZUC algorithm efficiently as well as reduce the hardware resources employment.

关 键 词：现场可编程门阵列 祖冲之算法 硬件实现 进位保留加法器 mod(231-1)加法器 

分 类 号：TP301.6[自动化与计算机技术—计算机系统结构]