一种基于FPGA的内容可寻址存储器的设计  

Design of Content Addressable Memory Based on Internal Registers in FPGA

作　　者：李训根[1] 罗霁[1] 

机构地区：[1]杭州电子科技大学电子信息学院,浙江杭州310018

出　　处：《杭州电子科技大学学报（自然科学版）》2014年第4期65-69,共5页Journal of Hangzhou Dianzi University：Natural Sciences

摘　　要：介绍了内容可寻址存储器的传统电路模型、工作原理及其特点,进而提出了一种基于FPGA内部逻辑资源的新型等效逻辑电路。相比现有电路,该电路可以通过分析实际需求的单位数据字长以及数据控制精度减少片内寄存器等逻辑资源的开销,从而实现使用较少的资源构建相同规模的内容可寻址存储器。该电路可以在绝大多数FPGA芯片上得到实现,使用成本低,配置灵活,易于构建。This paper introduces the classic circuit model, principles of work and characteristics of content addressable memory. A new equivalent logic circuit of content addressable memory （CAM） that is based on FPGA is proposed. It is indicated that in comparison with existed circuits, the new circuit decreases consumption of on-chip register and other logic resources by analyzing word sizes and accuracy of datum control in application, and thus less resources is required to implement content addressable memory at the same scale than other circuits do. This circuit could be implemented in a majority of FPGA chips, which costs low and is flexible in configuration and easy to construct.

关 键 词：内容可寻址存储器 现场可编程逻辑阵列 逻辑资源 等效逻辑电路 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]