基于FPGA与DSP的高速数字脉压的实现  

Implementation of High-speed Digital Pulse Compression Based on FPGA and DSP

作　　者：王涛[1] 徐晓理[1] 殷切[1] 

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《现代雷达》2014年第8期31-33,38,共4页Modern Radar

摘　　要：讨论了基于现场可编程门阵列(Field Programmable Gate Array,FPGA)与数字处理器(Digital Signal Processor,DSP)实现高速数字脉压的设计方法。将数字脉压分成距离快速傅里叶变换(Fast Fourier Transform,FFT)、复乘和距离快速傅里叶逆变换(Inverse Fast Fourier Transform,IFFT)三个模块,并将这三个模块在FPGA中利用定点算法实现。在实现时,每个模块均采用流水结构,200 MHz全局时钟,使数据通过率可以达到200MSPS(200 M复数点/s)。利用DSP实时生成脉压参考函数,并将其传输至FPGA中,用于信号复乘。通过对信号动态与精度的分析,基于FPGA与DSP的高速数字脉压完全可以满足系统要求,已经将其成功地应用于某型雷达的系统设计中。The design method of high-speed digital pulse compression based on FPGA and DSP is discussed in the article. Digital pulse compression is composed of three modules ： range FFT ,complex multiplication and range IFFT. These modules implement u- sing fixed point arithmetic ,pipeline configuration and 200 MHz global clock. The data rate could achieve 200 MSPS. The reference function of pulse compression is generated by DSP and transmitted to FPGA to achieve complex multiplication. Through analysis of signal dynamic range and accuracy, high-speed digital pulse compression based on FPGA and DSP could fulfill the need of radar system. This method is already applied successfully in certain radar system.

关 键 词：高速数字脉压 动态范围 精度 现场可编程门阵列 

分 类 号：TN957.51[电子电信—信号与信息处理]