AVAILABILITY MODEL FOR SELF TEST AND REPAIR IN FAULT TOLERANT FPGA-BASED SYSTEMS  

作　　者：Shampa Chakraverty Anubhav Agarwal Broteen Kundu Anil Kumar 

机构地区：[1]Division of Computer Engineering,Netaji Subhas Institute of Technology

出　　处：《Journal of Electronics(China)》2014年第4期271-283,共13页电子科学学刊（英文版）

摘　　要：Dynamically reconfigurable Field Programmable Gate Array(dr-FPGA) based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory. The aim of our research is to characterize self-test and repair processes in Fault Tolerant(FT) dr-FPGA systems in the presence of environmental faults and explore their interrelationships. We develop a Continuous Time Markov Chain(CTMC) model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test(BIST) and scrubbing to detect and repair faults with minimum latency. Simulation results reveal that given an average fault interval of 36 s, an optimum self-test interval of 48.3 s drives the system to spend 13% of its time in self-tests, remain in safe working states for 76% of its time and face risky fault-prone states for only 7% of its time. Further, we demonstrate that a well-tuned repair strategy boosts overall system availability, minimizes the occurrence of unsafe states, and accommodates a larger range of fault rates within which the system availability remains stable within 10% of its maximum level.Dynamically reconfigurable Field Programmable Gate Array （dr-FPGA） based electronic systems on board mission-critical systems are highly susceptible to radiation induced hazards that may lead to faults in the logic or in the configuration memory.The aim of our research is to characterize self-test and repair processes in Fault Tolerant （FT） dr-FPGA systems in the presence of environmental faults and explore their interrelationships.We develop a Continuous Time Markov Chain （CTMC）model that captures the high level fail-repair processes on a dr-FPGA with periodic online Built-In Self-Test （BIST） and scrubbing to detect and repair faults with minimum latency.Simulation results reveal that given an average fault interval of 36 s,an optimum self-test interval of 48.3 s drives the system to spend 13％ of its time in self-tests,remain in safe working states for 76％ of its time and face risky fault-prone states for only 7％ of its time.Further,we demonstrate that a well-tuned repair strategy boosts overall system availability,minimizes the occurrence of unsafe states,and accommodates a larger range of fault rates within which the system availability remains stable within 10％ of its maximum level.

关 键 词：Dynamically reconfigurable Field Programmable Gate Array （dr-FPGA） Built-In Self-Test （BIST） Fault Tolerance （FT） Single Event Effects （SEEs） Continuous Time Markov Chain （CTMC） ScrubbingCLC number：TN47 

分 类 号：TN47[电子电信—微电子学与固体电子学]