基于布线轨道的SoC芯片供电带设计优化  

Design Optimization of SoC Chip Power Straps Based on the Wire Tracks

作　　者：李虹杨 冯士维[1] 林平分[1] 万培元[1] 

机构地区：[1]北京工业大学电子信息与控制工程学院,北京100124

出　　处：《半导体技术》2014年第8期570-574,共5页Semiconductor Technology

基　　金：广东省战略新兴产业项目基金资助项目(2012A080304003)

摘　　要：针对传统用Synopsys公司IC Compiler工具自动生成供电带的设计方法会对布线资源产生一定程度的浪费,而影响物理设计布线质量的情况,提出了一种基于布线轨道的供电带设计优化方法。该方法在保证电压降的基础上,充分利用布线轨道,将供电带设计简化为两个参数的选取,同时推导出这两个参数与供电带占用布线轨道比例的关系公式,为后续设计流程留出足够的布线资源,提高芯片整体布线质量。将该方法用在一款采用TSMC 0.152μm Logic 1P5M CMOS工艺的电力载波通信芯片物理设计中,芯片数字规模约80万门。结果表明,在电压降保持稳定的情况下,释放了总共约300条布线轨道,为成功完成物理设计奠定了基础。The traditional design method for generating power straps automatically by the IC Compi ler tool of Synopsys causes great waste of routing resources, which influences the routing quality of the physical design. An optimization design method of power straps based on the wire track was proposed to solve the above issue. This method takes full advantage of the wire track to simplify the design of power straps into the selection of two parameters on the basis of ensuring the voltage drop, while the formula for the relationship between two parameters and the power straps with wire tracks proportion was derived, the method sets aside enough routing resources for the following design flow and improves the quality of the whole chip routing. The method was applied to the physical design of the power carrier communication chip with TSMC 0. 152 μm Logic 1PSM CMOS technology, the gate count for the design is about 0. 8 million. The results show that about 300 wire tracks are released in a context of the stable voltage drop, which lays the foundation for the successful completion of the physical design.

关 键 词：物理设计 布线轨道 供电带 供电网络 片上系统(SoC) 

分 类 号：TN402[电子电信—微电子学与固体电子学]