基于RC触发NMOS器件的ESD电路设计  

Design of the ESD Circuit Based on the RC Triggered NMOS Device

作　　者：李志国 余天宇 张颖 孙磊 潘亮 

机构地区：[1]北京中电华大电子设计有限责任公司,北京100102

出　　处：《半导体技术》2014年第8期579-583,共5页Semiconductor Technology

摘　　要：研究了基于电阻(R)电容(C)触发n型金属氧化物半导体(NMOS)器件的静电放电(ESD)电路参数与结构的设计,讨论了电阻电容触发结构对ESD性能的提升作用,研究了不同RC值对ESD性能的影响以及反相器结构带来的ESD性能差异,并讨论了在特定应用中沟道放电器件的优势。通过一系列ESD测试电路的测试和分析,发现电阻电容触发结构可以明显提高ESD电路的保护能力,其中RC值10 ns设计的栅耦合NMOS(GCNMOS)电路具有最高的单位面积ESD保护能力,达到0.62 mA/μm2。另外对于要求触发电压特别低的应用场合,RC值1μs设计的GCNMOS电路将是最好的选择,ESD能力可以达到0.47 mA/μm2,而触发电压只有3 V。The design of the circuit parameter and structure of the electro-static discharge （ESD） circuit based on the resistor capacitor （RC） , triggered NMOS devices were detailed studied. The improvement of the ESD performances by the RC triggering structure was discussed. The influences of different RC values and inverter structure on the ESD performances were specially investigated. The ad- vantage of the channel-discharge device was studied in some special applications. Through a series measurement and analysis of the ESD testing circuits, it was proved that the performance of the ESD circuit could be improved by the RC triggering structure. Among which, the gate coupled NMOS （GC- NMOS） with 10 ns RC has the best ESD protected capability of 0.62 mA/μm2. As for ultra-low trigger voltage requirement, the GCNMOS designed by 1 μs RC is the best choice, with the ESD protected capability of 0.47 mA/μm2 and a trigger voltage as low as 3 V.

关 键 词：互补型金属氧化物半导体(CMOS)工艺 电阻电容触发NMOS 静电放电(ESD)电路 传输线脉冲(TLP)测试 热效应 

分 类 号：TN432[电子电信—微电子学与固体电子学]