基于CPLD的4位数字频率计的设计与实现  

Design and Implementation of 4 Bit Digital Frequency Meter Based on CPLD

作　　者：周鹏[1] 孟晋[1] 孙荣庆[1] 

机构地区：[1]抚顺职业技术学院,辽宁抚顺113122

出　　处：《辽宁高职学报》2014年第6期81-83,共3页Journal of Liaoning Higher Vocational

摘　　要：随着电子设计自动化技术的不断提高,利用CPLD器件来实现各种数字系统,已经成为一种需要。为了提高数字频率计的精度与可靠性,提出采用Altera公司的EPM240T可编程逻辑器件对4位数字频率计进行设计。该数字频率计包括基准时钟模块、计数控制模块及显示输出模块三大部分。在设计过程中实现了硬件的系统与软件的功能,利用modelsim软件对频率计的功能进行仿真,结果准确;同时也对实际的外部信号进行了硬件系统测试,通过LED数码管读取到了准确的频率数据。With the development of electronic design automation, using CPLD devices to achieve a variety of digital systems has become a kind of need. In order to improve the accuracy and reliability of digital frequency meter, it puts forward the idea of using Altera＆#39;s CPLD for the design of 4 bit digital frequency meter. The digital frequency meter comprises a reference clock module, counting and controlling module, display and output module. In the design process, the hardware systemand the software function has been realized. It uses modelsim software to simulate the function of frequency meter, and the result is accurate; also external signal has been tested on the hardware system, the accurate data of frequency fromthe LED are also read.

关 键 词：数字频率计 CPLD 电子设计自动化 

分 类 号：TP311.53[自动化与计算机技术—计算机软件与理论]