行间转移型面阵CCD成像系统设计  

Design of imaging system of interline area CCD

作　　者：李亚鹏[1,2] 何斌[1] 付天骄[1] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所,吉林长春130033 [2]中国科学院大学,北京100049

出　　处：《红外与激光工程》2014年第8期2602-2606,共5页Infrared and Laser Engineering

基　　金：国家高技术研究发展计划(863-2-5-1-13B)

摘　　要：采用行间转移型面阵CCD KAI-1020作为图像传感器,以现场可编程门阵列(FPGA)为核心控制器,设计并实现了一个完整的成像系统。FPGA产生驱动时序、控制CCD上电顺序、调节曝光时间,并实现数据缓存。CCD模拟视频信号经过预处理,通过同轴电缆传输到CCD专用视频处理器进行相关双采样和模数转换,以10位像素深度输出到FPGA,数字视频信号经过差分芯片驱动以低压差分信号(LVDS)格式输出到数据采集卡。集成化视频处理电路提高了系统的信噪比,改善了成像质量。实验表明,CCD成像系统工作稳定可靠,像素读出时钟为10MHz时,帧频为10帧/s。设计的CCD成像系统性能好、可靠性高、实现周期短,具有很强的可扩展性。A complete imaging system was designed and implemented by using a interline CCD KAI- 1020 as image sensor. Field-Programmable Gate Array （FPGA） was adopted as the core controller of the whole system, which generated driving sequences, controlled the CCD power-up sequence, adjusted the exposure time and realized data cache. After preprocessing, CCD analog video output was transferred via coaxial cable to the dedicated CCD signal processor for correlated double sampling （CDS） and analog- digital conversion, and it finally outputted to FPGA in the form of 10-bit digital signal. CCD digital video signal was drove by differential line driver and then acquired by the image acquisition card in low voltage differential signaling （LVDS） format. The use of integrated CCD signal processor improved the system＇s signal to noise ratio and enhanced the image quality. Experimental results show that the designed CCD imaging system works normally and stably, the frame rate is 10 frames/s when the pixel readout clock is 10 MHz. The designed CCD imaging system characterizes good performance, high reliability, and short implementation cycle and provides high expansibility.

关 键 词：成像系统 行间转移型面阵CCD 驱动设计 视频处理 

分 类 号：TN386.5[电子电信—物理电子学] TN911.73