Investigation of the trigger voltage walk-in effect in LDMOS for high-voltage ESD protection  

作　　者：梁海莲 董树荣 顾晓峰 钟雷 吴健 于宗光 

机构地区：[1]Key Laboratory of Advanced Process Control for Light Industry (Ministry of Education), Department of Electronic Engineering, Jiangnan University [2]ESD Laboratory, Department of Information Science and Electronic Engineering, Zhejiang University [3]China Electronic Technology Group Corporation, No.58 Research Institute

出　　处：《Journal of Semiconductors》2014年第9期56-59,共4页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.61171038,61150110485);the Natural Science Foundation of Jiangsu Province(No.BK20130156);the Fundamental Research Funds for the Central Universities(Nos.JUSRP51323B,JUDCF13032);the Summit of the Six Top Talents Program of Jiangsu Province(Nos.DZXX-053 and DZXX-027);the Graduate Student Innovation Program for Universities of Jiangsu Province(No.CXLX13_747)

摘　　要：The trigger voltage walkin effect has been investigated by designing two different laterally diffused metal-oxide-semiconductor （LDMOS） transistors with an embedded silicon controlled rectifier （SCR）. By inserting a P＋ implant region along the outer and the inner boundary of the N＋ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5/zm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse （TLP） and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.The trigger voltage walkin effect has been investigated by designing two different laterally diffused metal-oxide-semiconductor （LDMOS） transistors with an embedded silicon controlled rectifier （SCR）. By inserting a P＋ implant region along the outer and the inner boundary of the N＋ region at the drain side of a conventional LDMOS transistor, we fabricate the LDMOS-SCR and the SCR-LDMOS devices with a different triggering order in a 0.5/zm bipolar-CMOS-DMOS process, respectively. First, we perform transmission line pulse （TLP） and DC-voltage degradation tests on the LDMOS-SCR. Results show that the trigger voltage walk-in effect can be attributed to the gate oxide trap generation and charge trapping. Then, we perform TLP tests on the SCR-LDMOS. Results indicate that the trigger voltage walk-in effect is remarkably reduced. In the SCR-LDMOS, the embedded SCR is triggered earlier than the LDMOS, and the ESD current is mainly discharged by the parasitic SCR structure. The electric potential between the drain and the gate decreases significantly after snapback, leading to decreased impact ionization rates and thus reduced trap generation and charge trapping. Finally, the above explanation of the different trigger voltage walk-in behavior in LDMOS-SCR and SCR-LDMOS devices is confirmed by TCAD simulation.

关 键 词：electrostatic discharge laterally diffused metal-oxide-semiconductor silicon control rectifier triggervoltage walk-in effect 

分 类 号：TN386[电子电信—物理电子学]