一种2.4GHz全集成双环路频率综合器的设计  

A 2.4 GHz Fully-Integrated CMOS Dual-Loop Frequency Synthesizer

作　　者：陈志华[1] 

机构地区：[1]南京陆军指挥学院,南京210045

出　　处：《电子器件》2014年第3期399-402,共4页Chinese Journal of Electron Devices

摘　　要：根据不同锁相环频率综合器架构各自的优缺点,选择了双环路锁相环结构以获得低相位噪声和快速锁定时间。采用0.18μm CMOS工艺设计了一款2.4 GHz全集成双环路锁相环频率综合器,由主锁相环和参考锁相环环路构成。采用MATLAB和SpectreRF对锁相环系统的相位噪声、锁定时间进行了仿真,得到主锁相环输出频率为在2.4 GHz时,相位噪声为-120 dBc/Hz@1 MHz,功耗为10 mW,电源电压为1.8 V。频率范围为2.4 GHz至2.5 GHz,RMS相位误差为1°,锁定时间为5μs。According to the performances of the different architectural choices available for the frequency synthesizer are compared. The dual-loop frequency synthesizer is chosen for its low phase noise and fast lock time. A 2.4 GHz fully integrated dual-loop frequency synthesizer is designed by a 0. 18 μm CMOS process for wireless communication, comprised a main PLL and a Reference PLL. The phase noise and locked time performance of the PLL is simulated by MATLAB and SpectreRF,the main PLL＇s LC-VCO operates at 2.4 GHz with the phase noise of -120 dBc/Hz@ 1 MHz. The power consumption is 10mW under a 1.8 V power supply voltage. The PLL output frequency range is from 2.4 GHz to 2.5 GHz. The simulated RMS phase error is 1 ° and the lock time is 5 μs.

关 键 词：锁相环频率综合器 低相位噪声 双环路结构 锁定时间 

分 类 号：TN47[电子电信—微电子学与固体电子学]