基于拼接采样技术的宽带数字接收机  

A Wideband Digital Receiver Based on Time-Interleaved Sampling Technique

作　　者：向海生[1] 马利祥[1] 王冰[1] 

机构地区：[1]中国电子科技集团公司第三十八研究所,安徽合肥230088

出　　处：《雷达科学与技术》2014年第4期450-453,共4页Radar Science and Technology

摘　　要：宽带数字接收机是当前的一个研究热点。介绍一个基于拼接采样技术的双通道宽带数字接收机设计及实现,描述了接收机的硬件架构、固件设计要点、拼接采样误差校正方法和指标测试结果。接收机采用商用货架器件和标准的FPGA夹层卡架构,结合拼接采样和宽带数字下变频技术进行设计,具有接收瞬时信号带宽大,预处理运算能力强,数据传输带宽大、硬件兼容性及扩展性好等特点,能广泛应用于宽带通信、雷达及电子战系统中。Wideband digital receiver has become a research focus. This paper introduces the design and implementation of a two-channel wideband digital receiver based on time-interleaved sampling technique. The hardware architecture of the receiver, the keystone of firmware design, the correction method of time-interleaved sampling errors and the performance test results are described. The design of receiver adopts the COTs（commercial-off-the-shelf） devices and standard FMC（FPGA Mezzanine Card） architecture and integrates with time-interleaved sampling and wideband digital down conversion techniques. The receiver is characterized by large instantaneous bandwidth of the received signal, strong pre-processing operation capability, large data transmission bandwidth, and good hardware compatibility and scalability. It can be widely used in wideband communication, radar, and electronic warfare systems.

关 键 词：宽带 数字接收机 拼接采样 数字下变频 FPGA夹层卡 

分 类 号：TN957.51[电子电信—信号与信息处理]