Mixed-Level Modeling Methodology for Network-on-Chip Architecture Exploration  

作　　者：YIN Shouyi ZHANG Zhen HU Yang LIU Leibo WEI Shaojun 

机构地区：[1]Institute of Microelectronics,Tsinghua University [2]National Laboratory for Information Science and Technology,Tsinghua University

出　　处：《Chinese Journal of Electronics》2014年第3期468-473,共6页电子学报（英文版）

基　　金：supported by the China Major Science and Technology Project(No.2013ZX01033001-001-003);the International Science and Technology Cooperation Project of China(No.2012DFA11170);the Tsinghua Indigenous Research Project(No.20111080997);the National Natural Science Fundation of China(No.61274131)

摘　　要：As Network on chip(NoC) architecture develops as an solution of interconnection in System on chip(SoC) designs, a detailed and flexible interconnection network model integrated in a full system evaluation framework becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification platform. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time, bus phase transaction level which intend to gain higher simulation speed, and lower step to relative development of software. The experimental results show that the mixedlevel NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.As Network on chip （NoC） architecture de- velops as an solution of interconnection in System on chip （SoC） designs, a detailed and flexible interconnection net- work model integrated in a full system evaluation framework becomes necessary. In this paper, we first present a mixed abstraction level modeling methodology for the performance evaluation of NoC architecture. Then based on our mixed level modeling methodology, we develop a full system mixed-level NoC evaluation and verification plat- form. Aiming to explore the details of the performance evaluation and hardware verification of interconnection part, we build NoC router at cycle-accurate, bus cycle level and build SoC peripherals at approximately time~ bus phase transaction level which intend to gain higher simulation speed, and lower step to relative development of software. The experimental results show that the mixedlevel NoC evaluation platform can achieve both detailed architecture exploration and fast simulation speed.

关 键 词：Mixed-level modeling Transaction-level modeling NETWORK-ON-CHIP SoC design. 

分 类 号：TN47[电子电信—微电子学与固体电子学]