多层铁电薄膜存储二极管的界面内建电压  

Built-in Voltage at Interface of the Multilayer Ferroelectric Films

作　　者：李兴教[1] 王宁章[1] 鲍军波[1] 陈涛[1] 冯汉华[1] 袁润章[2] LI Shao-ping 

机构地区：[1]华中科技大学电子系,武汉430074 [2]武汉理工大学,武汉430070 [3]Advanced Recording Technology Laboratory

出　　处：《压电与声光》2002年第4期292-294,共3页Piezoelectrics & Acoustooptics

基　　金：国家自然科学基金资助项目 (5 9972 0 10 ) ;武汉理工大学材料复合新技术国家重点实验室资助项目

摘　　要：利用准分子激光在 p型硅薄片上淀积了多层铁电薄膜 BIT/ PZT/ BIT、PZT/ BIT和 BIT。讨论了多层铁电薄膜界面内建电压 ,其中 Au/ BIT/ PZT/ TBIT/ p- Si(10 0 )的 ΔVb 最小而 Au/ BIT/ p- Si(10 0 )的 ΔVb 最大 ,但Au/ BIT/ PZT/ TBIT/ p- Si(10 0 )的ΔVb 与 Au/ BIT/ p- Si(10 0 )的Δ Vb 相差不多。 Au/ BIT/ PZT/ TBIT/ p- Si(10 0 )的I- V特性曲线非对称的整流特性和 P- V回线的刻印失效是最小的而 Au/ BIT/ p- Si(10 0 )Ferroelectric BIT/PZT/BIT,and PZT/BIT,and BIT multilayer ferroelectric thin films were deposited on(100)p type wafers by pulsed excimer laser the built in voltages at the interface of the multilayer ferroelectric films were discussed three structure capacitors have three different Δ V b,among the three structures,the Δ V b,of the Au/BIT/PZT/TBIT/p Si(100) is the smallest and the Δ V b of the Au/BIT/p Si(100)is the largest,the value of Au/PZT/TBIT/p Si(100) is about the same of Au/PZT/p Si(100) The asymmetric degree of rectification behavior of I V curve,and an in imprint failure of P V loop of Au/BIT/PZT/TBIT/p Si(100) were the smallest and that of the Au/BIT/p Si(100) were the largest

关 键 词：多层铁电薄膜 内建电压 刻印失效 整流特性 半导体存储器 

分 类 号：TN304.9[电子电信—物理电子学] TP333[自动化与计算机技术—计算机系统结构]