低存储高速可重构LDPC码译码器设计及ASIC实现  

Design and ASIC Implementation of Low Memory High Throughput Reconfigurable LDPC Decoder

作　　者：栾志斌[1] 裴玉奎[1] 葛宁[1] 

机构地区：[1]清华大学信息科学与技术国家实验室,北京100084

出　　处：《电子与信息学报》2014年第10期2287-2292,共6页Journal of Electronics & Information Technology

基　　金：国家自然科学基金(61132002;61301079;91338103);北京高等学校青年英才计划项目;清华大学自主科研项目(2011Z05117)资助课题

摘　　要：在星上应用中,能够融合多种标准的可重构低密度奇偶校验(LDPC)码译码器受到越来越广泛地关注。然而,由于星上存储资源受限以及空间辐射效应对存储器的影响,传统需要消耗大量存储资源的可重构LDPC译码器很难适用于星上高速信号处理。该文提出一种新颖的可重构译码器架构,通过分层流水线迭代实现高吞吐率,通过结合不同LDPC码字的结构特点实现低复杂度的可重构译码,通过简化存储迭代传递信息以及信道对数似然比(LLR)信息节省存储空间。流片实现结果表明,在台积电(TSMC)0.13 mm工艺下,单路译码器最高可达1.5 Gbps的吞吐率,占用7.8 mm2的硅片面积,最高节省40%的存储资源。Reconfigurable Low-Density Parity-Check （LDPC） codes decoders adapted to multiple standards attracte more and more attentions in thesatellite application. However, due to the memory resource is limited on the satellite and sensitive to the space radiation effect, the conventional reconfigurable decoders are difficult to be applied to on-board processing for their high memory requirements. This paper presents a novel reconfigurable decoder with layered pipelined architecture to achieve high throughput and realizes low complexity by combining the structural characteristics of different LDPC codes. The memory size is reduced by simplifying the storage of the channel intrinsic Logarithm Likelihood Ratio （LLR） messages and the passed messages in the process of iterative decoding. The decoder is fabricated in the TSMC 0.13mm standard CMOS technology and the result shows that each branch can achieve a throughput up to 1.5 Gbps with 7.8 mm2 core area occupancy and can save 40%storage resource at most.

关 键 词：低密度奇偶校验(LDPC)码 无线通信 可重构 低存储 高吞吐率 专用集成电路(ASIC) 

分 类 号：TN911.22[电子电信—通信与信息系统]