基于硬件复用的RS编码与译码体系结构  

RS encoding and decoding architecture based on hardware reusability

作　　者：潘红兵[1] 席泽敏[1] 谭思炜[1] 

机构地区：[1]海军工程大学电子工程学院,武汉430033

出　　处：《海军工程大学学报》2014年第5期88-91,共4页Journal of Naval University of Engineering

摘　　要：基于FPGA可重复配置原理,提出了一种硬件复用的RS码编码译码体系结构,用以解决传统RS码编译码器实现方式硬件资源消耗量大的问题。该编译码器中的可重构计算模块可根据配置信息改变逻辑电路结构,满足编码和译码过程中不同算法的计算需要。最后,采用VHDL实现了以上编译码器,并在Quartus II中进行了综合验证。结果表明:该编译码器能满足多种纠错能力的RS码编译码,通过硬件复用技术可提高硬件资源利用效率。Based on the principle of FPGA reconfiguration, an architecture of hardware reusability is proposed for RS encoding and decoding, with the aim of solving the problem of high consumption of hardware resources by the traditional RS codec architecture. The logic circuit of the reconfigurable computing module in the codec can be changed according to the configuration information to meet the needs of different algorithms during the encoding and decoding process. The RS codec is acquired by VHDL and tested by Quartus Ⅱ. The results indicate that the codec can satisfy a variety of errorcorrecting capabilities in RS decoding and encoding, improve the usability of hardware resources by the hardware reusable technique.

关 键 词：硬件复用 FPGA RS编译码器 

分 类 号：TN492[电子电信—微电子学与固体电子学]