A 14.5Gb/s word alignment circuit in 0.18μm CMOS technology for high-speed SerDes  

作　　者：阮伟华 Hu Qingsheng 

机构地区：[1]Institute of RF-&OE-lCs,Southeast University

出　　处：《High Technology Letters》2014年第3期328-332,共5页高技术通讯（英文版）

基　　金：Supported by the National High Technology Research and Development Programme of China(No.2011AA10305)

摘　　要：This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 ×0.775mm^2￣ including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.This paper presents a word alignment circuit for high speed SerDes system.By using pipeline structure and circuit optimization techniques,the speed of the aligner is increased,and its performance is improved further through adopting the full custom design method.The proposed word aligner has fabricated in 0.18μm CMOS technology with total area of 1.075 × 0.775mm2 including I/O pad.Measurement results show that this circuit achieves the maximum data rate of 14.5Gb/s,while consuming a total power of 34.9mW from a 1.8V supply.

关 键 词：comma detection word alignment PIPELINE full custom parallel structure 

分 类 号：TN405[电子电信—微电子学与固体电子学]