一种应用于超高速ADC中6G/8GHz的高精度正交时钟产生电路  

A Clock Generator with Accurate Quadrature Output Phases for High Speed ADC Application

作　　者：蒋健兵[1] 马顺利[1] 周光耀[1] 叶凡[1] 任俊彦[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2014年第4期458-465,474,F0002,共10页Journal of Fudan University：Natural Science

基　　金：国家高技术研究发展计划(2013AA013101)资助项目

摘　　要：正交时钟被广泛地用在正交频分复用（OFDM）通信系统的时间交织模拟数字转换器（ADC）中.正交信号的相位偏差和时钟抖动对整个系统都有着重要的影响.针对时间交织ADC的应用需求,提出一种宽带的输出相位可调的正交注入锁定分频器,通过调节注入信号和耦合信号的能量来改善因器件失配和工艺偏差等造成的正交信号的相位误差.在此基础上设计了一个基于LC压控振荡器的电荷泵型锁相环.该锁相环采用TSMC65nm工艺设计,正交时钟的频率输出范围是5.8-6.5GHz和7.1-8.3GHz,正交相位的平均误差小于0.26°,满足系统设计的预设指标.Quadrature clock was widely used in OFDM communication systems,time-interleaved ADC and other fields.Phase mismatch and clock jitter of a quadrature signal seriously deteriorate the performance of ADC system.According to the time-interleaved ADC＇s requirement,a wideband quadrature Injection-Locked frequency divider with tunable output phases is proposed.It shows that the quadrature phase error caused by devices mismatch and process variation can be ameliorated by tuning the power of injected and coupled signals.Based on this,aphaselocked loop with a LC VCO is designed.The proposed PLL was designed in TSMC 65 nm CMOS process.Post simulation results show that the output quadrature signals have a tuning range from 5.8—6.5GHz and 7.1—8.3GHz.The average phase error is below 0.26 degree.

关 键 词：锁相环 正交时钟 相位可调 注入锁定分频器 

分 类 号：TN402[电子电信—微电子学与固体电子学]