层次化片上多核处理器性能研究  

Performance analysis of hierarchical chip multicore processor

作　　者：侯宁[1] 赵红梅[1] 宋宇鲲[2] 

机构地区：[1]河南城建学院电气与信息工程系,河南平顶山467000 [2]合肥工业大学微电子设计研究所,安徽合肥230009

出　　处：《合肥工业大学学报（自然科学版）》2014年第10期1226-1230,共5页Journal of Hefei University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(61179036;61106020)

摘　　要：层次化片上多核处理器紧耦合多个处理核构成"簇节点",对访存和片上通信的局部性有良好支撑,能有效地缓解片上多核间数据通信带来的通信开销。文章通过构建精细的层次化片上多核处理器仿真器,利用随机任务模型研究"簇节点"大小对系统性能的影响。仿真发现,一定系统规模下,要获得良好的系统性能,层次化片上多核处理器需要在"簇节点"数目与"簇节点"的大小(节点内处理核的数目)之间仔细权衡。Hierarchical chip multicore processor（HCMP） can well support the memory access and on-chip communication locality through cluster node ,each of w hich consists of several tightly coupled processing cores ,thus efficiently reducing the data communication latency .In this paper ,a C＋ ＋based cycle-accurate simulation model is established ,and the influence of processing core number in each cluster node on HCMP performance is studied by using stochastic task model .The simulation re-sults show that under certain system scope ,in order to achieve high performance of HCM P ,the con-figuration of the cluster node number and processing core number in each cluster node should be care-fully considered .

关 键 词：层次化结构 片上多核处理器 建模 性能分析 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]