考虑NBTI空穴俘获释放机制的组合逻辑门延迟预测  

Combination gate delay prediction considering NBTI hole trapping/detrapping mechanism

作　　者：李军[1] 梁华国[1,2] 许达文 靳松[3] 

机构地区：[1]合肥工业大学计算机与信息学院,合肥230009 [2]合肥工业大学电子科学与应用物理学院,合肥230009 [3]华北电力大学电气与电子工程学院电子与通信工程系,保定071003

出　　处：《中国科学：信息科学》2014年第10期1264-1272,共9页Scientia Sinica(Informationis)

基　　金：国家自然科学基金(批准号:61274036;61371025;61204027)资助项目

摘　　要：随着集成电路工艺尺寸下降到纳米级,负偏置温度不稳定性(NBTI)成为影响电路可靠性的首要老化效应.精确的老化预测模型是节省防护开销的重要前提.针对已有反应扩散机制下阈值电压变化预测模型存在的预测偏差问题,本文分析了NBTI空穴俘获释放机制下阈值电压变化模型,提出了新的组合逻辑门传输延迟预测模型(TDDP),达到了更精确预测数字电路老化的目的,为老化防护提供了更优的参考模型.实验结果表明,针对设置时序余量的老化防护方法,在保证10年等值生命周期可靠性的前提下,参考TDDP模型比参考已有的RD延迟模型减少平均17.8%的时序余量开销.With aggressive scaling of the feature size, randomness in negative bias temperature instability （NBTI） process poses a dramatic challenge on reliability prediction of digital circuits. Accurate statistical aging prediction is essential for developing accurate guard banding and protection strategies during the design stage. The existing gate delay prediction model is strongly dependent of time constant, resulting in inaccurate aging degree. By analyzing the transistor threshold voltage variation model under NBTI trapping/detrapping mechanism, we propose a novel delay model named tapping/detrapping based delay- prediction （TDDP） for the combination gates. TDDP achieve to reduce the costs of timing margin. Experimental results show that, considering TDDP call save 17.8% timing margin during tile design stage of the circuit, compared with the traditional prediction model of gate propagation delay considering reaction diffusion mechanism.

关 键 词：老化 负偏置温度不稳定性 门延迟 模型 关键路径 

分 类 号：TN386[电子电信—物理电子学]