基于时分复用技术的低功耗数据总线FV-BI自适应编码  

Low-power data bus FV-BI adaptive coding based on time division multiplexing technique

作　　者：王新胜[1] 韩良[1] 喻明艳[1] 

机构地区：[1]哈尔滨工业大学航天学院,黑龙江哈尔滨150001

出　　处：《系统工程与电子技术》2014年第11期2320-2325,共6页Systems Engineering and Electronics

基　　金：国家自然科学基金(61201307)资助课题

摘　　要：对频率值（frequent value,FV）编码技术进行了改进,并结合总线反转（bus invert,BI）编码技术的优点提出了FV-BI自适应总线编码,利用时分复用技术解决了多套数据总线混合编码问题和需要两根额外数据线问题。基于基准测试程序、图片及音视频和随机数的测试,结果表明提出的FV-BI自适应总线编码技术能降低22%-53%的开关活动,相比单独FV编码和BI编码技术开关活动降低2-4倍。利用Matlab软件和PrimePower软件,在0.18μm工艺下针对不同互连线长度进行行为级和sign-off级功耗估计,结果表明在接近10mm互连线长度下,FV-BI自适应编码技术能有效降低芯片功耗。最后完成了FV、BI和FV-BI自适应编码技术在现场可编程门阵列（field programmable gate array,FPGA）的实现,利用Xpower软件分析其功耗,并进行FPGA板级测试,结果也证明了FV-BI编码技术降低功耗的有效性。By combining the advantage of the improved frequent value （FV）and bus invert （BI）coding techniques,the FV-BI adaptive bus coding is proposed,which mainly uses time division multiplexing technique to solve multiple sets of data bus coding and two additional data line problems.Experiment results show that FV-BI coding yields a 22% 53% reduction in data bus switching activity for benchmark programs in addition picture, audio/video and random testing data.Moreover the reduction in switching activity by FV-BI is 2 4 times the reduction achieved by BI and FV alone.Meanwhile the power estimation of system level and sign-off level by Matlab and PrimePower program in 0.18 μm process technology is given.The results in 10 mm interconnect length show that the FV-BI adaptive coding technique can effectively reduce the power of chip.Finally,the FV,BI and FV-BI coding techniques are implemented in field programmable gate array （FPGA）and evaluate the power based on Xpower program and board testing.The results also show that FV-BI coding scheme is effectively reduced the power of interconnect system.

关 键 词：频率值总线反转编码 低功耗 总线编码 时分复用技术 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]