8～25 GHz 1:8高速分频器的设计  

Design of 8～25 GHz High Speed 1:8 Frequency Divider

作　　者：张楠[1] 陆泼 苏浩[1] 石春琦[1] 张润曦[1] 

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200062

出　　处：《微电子学》2014年第5期670-674,共5页Microelectronics

基　　金：上海市科技创新行动计划(13511500702);复旦大学专用集成电路与系统国家重点实验室开放课题(10KF013);中国科学院上海微系统所无线传感器网络与通信重点实验室开放课题

摘　　要：采用IBM0.13μm CMOS工艺,在锁相环系统电源电压2.5V的条件下,以三级分频器级联的方式实现了一款8-25GHz 1∶8高速分频器电路。为了获得更高的工作速度和灵敏度,设计中对传统的伪差分结构锁存器进行了拓扑和版图优化,基本的二分频单元由锁存器和输出缓冲级电路构成,以保证版图布线后信号传输的衰减最低。后仿真结果表明：在电源电压2.5V时,分频器的核心电路（第一级）功耗为21.75mW,对应的版图尺寸为70μm×35μm;在输入信号峰峰值900mV的条件下,分频范围达到8-25GHz,并通过了所有工艺角和温度仿真。A 8-25 GHz high speed 1 ： 8 frequency divider was implemented based on IBM 0.13 μm CMOS process with the method of three stage cascade at 2.5 V supply voltage of the phase locked loop. In order to obtain higher operating frequency and sensitivity, the traditional pseudo differential structure was improved and the layout was optimized. The basic dividing unit consisted of latch circuit and buffer to ensure the minimum attenuation of signal transmission after layout routing. The post simulation results showed that the power consumption of first stage was 21.75 mW at 2.5 V supply voltage and the corresponding pattern size was 70 μm×35μm. The dividing frequency range was 8-25 GHz at 900 mV （p-p） input signal. All corner and temperature simulations had been verified.

关 键 词：CMOS PLL 高速分频器 伪差分结构 

分 类 号：TN432[电子电信—微电子学与固体电子学]