锁相频率源混频信号的相位噪声分析  

Phase Noise Analysis of Phase-locked Loops Connecting to a Mixer

作　　者：潘碑[1] 苏卫国[1] 

机构地区：[1]南京电子器件研究所,南京210016

出　　处：《固体电子学研究与进展》2014年第5期432-435,439,共5页Research & Progress of SSE

摘　　要：分析了锁相源的相位噪声构成,并在此基础上建立了两路相关锁相源混频相位噪声的近似数学模型,推导了相应的相位噪声的计算式。通过实验及对实验数据的分析表明,该数学模型与实际实验结果一致,大幅度减小了相位噪声估计的偏差。该数学模型能有效的指导复杂频率源的设计及相位噪声的估算。The phase noise of phase-locked loops（PLLs）is studied.A mathematical model of phase noise of two correlated PLLs connecting to a mixer is presented,which allows designers to use the equations to evaluate the phase noise.Finally,the model calculated results have been compared with measured results obtained from actual PLLs connecting to a mixer,showing good effectiveness of the proposed model and equations.The mathematic model can help design the complex frequency synthesizers and evaluate the phase noise effectively.

关 键 词：锁相频率源 相位噪声 混频 

分 类 号：TN74[电子电信—电路与系统]