Process techniques of charge transfer time reduction for high speed CMOS image sensors  

作　　者：曹中祥 李全良 韩烨 秦琦 冯鹏 刘力源 吴南健 

机构地区：[1]State Key Laboratory of Superlattices and Microstructures,Institute of Semiconductors,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2014年第11期90-97,共8页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61234003);the Special Funds for Major State Basic Research Project of China(No.2011CB932902)

摘　　要：This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode （PPD） and the voltage difference between the PPD and the floating diffusion （FD） node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode （PPD） and the voltage difference between the PPD and the floating diffusion （FD） node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

关 键 词：CMOS image sensors high speed large-area pinned photodiode charge transfer time doping concentration depletion mode transistor 

分 类 号：TP212[自动化与计算机技术—检测技术与自动化装置]