基于FPGA的储存环束流轨道联锁系统设计  

FPGA-based storage ring beam orbit interlock system design

作　　者：耿合龙 冷用斌[1] 周伟民[1] 赖龙伟[1] 阎映炳[1] 

机构地区：[1]中国科学院上海应用物理研究所,上海201800 [2]中国科学院大学,北京100049

出　　处：《强激光与粒子束》2014年第12期240-244,共5页High Power Laser and Particle Beams

基　　金：国家自然科学基金项目(11105211;11305253;11375255)

摘　　要：上海光源储存环束流轨道联锁系统是加速器机器联锁保护系统(MPS)的重要组成部分,针对日常供光和机器研究的需求,需要对束流位置测量系统前各Libera电子学输出的联锁信号进行标记,以区分联锁信号的先后顺序和误报的联锁信号,同时触发所有Libera电子学前锁存逐圈(TBT)数据。新的联锁系统将所有联锁信号通过光纤传输汇总至FPGA数据采集板卡进行甄别,并将该系统集成储存环EPICS控制系统中。实验室测试显示该系统能够能够分辨数十ns范围内模拟的联锁信号,同时输出特定的触发信号至对应的Libera电子学,表明该系统达到设计要求。The beam orbit interlock system is one of the most important components of the machine protection system （MPS） of Shanghai Synchrotron Radiation Facility（SSRF）. The daily research asks for recording the interlock signal coming from different Libera BPM in the beam position measurement system, and lathing turn by turn data in Post Mortem buffer in Libera e lectronics when interlock occurs. This will be helpful to distinguish mistaken interlock signal and improve the stability of the ac celerator. In our system, we use NI PXI-7813R DAQ equipment based on FPGA to achieve these functions. This system will be integrated to EPICS control system. The laboratory test results show that the system is able to distinguish the simulated interlock signal in the range of tens of nanoseconds, and output specific trigger signal to the corresponding Libera electronics, which prove that the system meets the designed requirements.

关 键 词：上海光源 束流测量 轨道联锁 

分 类 号：TL506.6[核科学技术—核技术及应用]