100Gb/s在线网络安全处理器的10Gb/sIP核  被引量:1

10Gb/s IP-core for a 100Gb/s in-line network security processor

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作  者:牛赟[1] 乌力吉[1] 刘洋[1] 张向民[1] 

机构地区:[1]清华大学微电子研究所,清华大学信息科学与技术国家实验室,北京100084

出  处:《清华大学学报(自然科学版)》2014年第9期1230-1235,共6页Journal of Tsinghua University(Science and Technology)

基  金:核高基重大专项(2011ZX01034-002-002-003)

摘  要:为解决高速网络中的信息安全问题,设计实现了一种用于100Gb/s在线网络安全处理器中的单通道10Gb/s在线网络安全处理IP核,并在65nm CMOS工艺下流片验证。提出了基于中断的二级缓冲高速数据包收发机制,实现对可变长度数据包的均衡分配;通过改进交叉开关中的iSLIP调度算法,片上资源利用率达到86.6%;提出了一种快速低功耗数据库查找方法,查表速率达到11.9Gb/s。芯片集成了单通道10Gb/s高速串口、16个IPSec AH协议处理模块和16个HMAC-SHA-1认证算法模块及控制器,面积为2.4mm×3.1mm,规模为370万门。在自主设计的测试平台上的测试结果表明:单通道10Gb/s高速串口在10Gb/s传输速率及PRBS 27-1前提下,误码率达到10-13;IPSec协议处理与密码算法组成的异质多核部分在200MHz工作频率下,AH协议传输模式下的数据吞吐率满足设计要求。A 10 Gb/s in-line network security processing IP core design was developed for a 100 Gb/s in-line network security processor (NSP) and verified on 65 nm CMOS for improved information security in high-speed networks. The core uses a two-stage buffering mechanism based on interrupts that significantly reduces the changeable length packet loss rate. The configurable crossbar data transfer skeleton with a modified iSLIP scheduling algorithm increases the utilization rate of the parallel hetero-multi-core computational resources to 86%. The high-speed and low-power look-up method is used with look-up speed up to 11.9 Gb/s. The verified chip integrates a single channel 10 Gb/s SerDes, 16 AH cores, 16 HMAC-SHA-1 cores and the controller. The area is 2.4mm×3.1mm with 3.7 million gates. The chip was tested on a single channel 10 Gb/s high speed test platform. The results show that the error count for the single channel 10 Gb/s SerDes with data rates of 10 Gb/s and PRBS27-1 is 10da and the data throughput in the AH transport mode satisfies the 10 Gb/s in-line requirement for a clock rate of 200 MHz. The design can be used as a key IP-core in the 100 Gb/s NSP to realize 100 Gb/s in-line security processing.

关 键 词:网络安全处理器 网络安全协议 10Gb/s高速串口 密码算法 

分 类 号:TN918.91[电子电信—通信与信息系统]

 

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