Retention Benefit Based Intelligent Cache Replacement  

作　　者：李凌达 陆俊林 程旭 

机构地区：[1]CCF [2]ACM [3]Microprocessor Research and Development Center,Peking University [4]Engineering Research Center of Microprocessor and System,Ministry of Education [5]School of Electronics Engineering and Computer Science,Peking University

出　　处：《Journal of Computer Science & Technology》2014年第6期947-961,共15页计算机科学技术学报（英文版）

基　　金：supported in part by the National Science and Technology Major Project of the Ministry of Science and Technology of China under Grant No.2009ZX01029-001-002-2

摘　　要：The performance loss resulting from different cache misses is variable in modern systems for two reasons： 1） memory access latency is not uniform, and 2） the latency toleration ability of processor cores varies across different misses. Compared with parallel misses and store misses, isolated fetch and load misses are more costly. The variation of cache miss penalty suggests that the cache replacement policy should take it into account. To that end, first, we propose the notion of retention benefit. Retention benefits can evaluate not only the increment of processor stall cycles on cache misses, but also the reduction of processor stall cycles due to cache hits. Then, we propose Retention Benefit Based Replacement （RBR） which aims to maximize the aggregate retention benefits of blocks reserved in the cache. RBR keeps track of the total retention benefit for each block in the cache, and it preferentially evicts the block with the minimum total retention benefit on replacement. The evaluation shows that RBR can improve cache performance significantly in both single-core and multi-core environment while requiring a low storage overhead. It also outperforms other state-of-the-art techniques.The performance loss resulting from different cache misses is variable in modern systems for two reasons： 1） memory access latency is not uniform, and 2） the latency toleration ability of processor cores varies across different misses. Compared with parallel misses and store misses, isolated fetch and load misses are more costly. The variation of cache miss penalty suggests that the cache replacement policy should take it into account. To that end, first, we propose the notion of retention benefit. Retention benefits can evaluate not only the increment of processor stall cycles on cache misses, but also the reduction of processor stall cycles due to cache hits. Then, we propose Retention Benefit Based Replacement （RBR） which aims to maximize the aggregate retention benefits of blocks reserved in the cache. RBR keeps track of the total retention benefit for each block in the cache, and it preferentially evicts the block with the minimum total retention benefit on replacement. The evaluation shows that RBR can improve cache performance significantly in both single-core and multi-core environment while requiring a low storage overhead. It also outperforms other state-of-the-art techniques.

关 键 词：retention benefit REPLACEMENT last-level cache 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]