一种面向高性能计算的多FPGA互连结构及划分方法  

Hierarchical routing architecture and partitioning approach for multiple FPGAs oriented to high performance computing

作　　者：肖春华[1] 黄樟钦[1] 李达[1] 

机构地区：[1]北京工业大学嵌入式软件与系统研究所,北京100022

出　　处：《计算机应用研究》2015年第1期150-155,共6页Application Research of Computers

基　　金：北京市自然科学基金资助项目(4122010)

摘　　要：针对高性能计算系统在大规模通信互连中面临的性能、成本及功耗等问题,融合新兴的高速互连技术,结合大规模、超大规模系统通信的局部性和异构性,提出基于多FPGA的混合层级高速互连结构,并给出基于集群的多FPGA逻辑功能划分方法。该方法能够根据不同应用自定义设计高效互连网络,降低大规模计算系统的互连成本和开销。通过应用实例实验证明,该方法能够实现大规模设计向多FPGA高性能计算平台的快速映射,加速高性能可配置计算系统的设计实现。To target the problems of performance, cost and energy consumption in large scale communications of high perfor- mance computing, this paper proposed a hierarchical routing architecture and partitioning approach for muhiple FPGAs. This method compromised the merits of emerging high performance interconnects, and exploited the local and hierarchical properties of future large scale communications. The proposed approach could design the customized interconnect topology according to different applications to reduce the interconnect cost while keep the high performance. This approach can implement the fast mapping from the design to the real high performance computing system with multi-FPGAs, and accelerate the realization of high performance reconfigurable computing systems.

关 键 词：高性能计算 多FPGA系统 逻辑资源划分 高性能互连 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]