SoC总线的低功耗分支编码方案  

Low power branch encoding scheme based on So C bus

作　　者：李栋[1] 王小力[1] 杨斌[1] 赵长睿 

机构地区：[1]西安交通大学电子与信息工程学院,西安710049 [2]北京大学软件与微电子学院,北京100871

出　　处：《计算机应用》2014年第12期3633-3636,共4页journal of Computer Applications

基　　金：国家自然科学基金资助项目(61172041)

摘　　要：为了降低So C总线功耗,提出一种总线低功耗分支编码。该编码的基本思想为:对于地址总线,当地址连续时将地址总线死锁,当地址不连续时动态地调整窗口大小对其进行翻转编码;对于数据总线,对不同数据位宽分别设置两个汉明距阈值,当汉明距落在两个阈值之间则查找有效数据通道翻转密集区并对该区取反,两个阈值之外则采用翻转编码。该方法的编解码电路在32位AHB总线系统上实现,实验证明该方法与未编码之前相比将地址总线跳变率降低了51.2%,数据总线跳变率降低了22.4%,系统总功耗降低了28.9%。将T0编码、BI编码等方法在相同系统下实现后与所提方法作比较,证明分支编码方法在降低跳变率和功耗上有明显的优势。A low power branch encoding method was presented for decreasing the SoC bus power dissipation. This method＇ s basic principle is： for the address bus, when the address bus is sequential, the address bus is frozen, and when the address bus is non-sequential, the window size is adjusted dynamically to apply the Bus-Invert （BI） method on the address bus. For the data bus, two threshold values are figured out for different data size respectively. If the Hamming distance locates between these two threshold values, the valid-data-channel switching dense area is found and inverted, otherwise applies the BI encoding. This method＇ s encoding and decoding circuits are realized in the Advanced High Performance Bus （AHB） system. The experimental result demonstrates that compared with uncoded situation, this method decreases the address/data bus toggle rate by 51.2%/22.4%, and the system power is reduced by 28.9%. Compared with TO, BI and other encoding methods realized in the same system, the branch encoding is more superior in the toggle rate and power dissipation.

关 键 词：分支编码 总线编码 低功耗 高级高性能总线 跳变率 

分 类 号：TP331.1[自动化与计算机技术—计算机系统结构]