A low-power,area-efficient all-digital delay-locked loop for DDR3 SDRAM controller  

作　　者：CHEN HongMing MA Song WANG Liu ZHANG Hao PAN KenYi CHENG YuHua 

机构地区：[1]Shanghai Research Institute of Microelectronics (SHRIME), Peking University [2]School of Electronics Engineering and Computer Science, Peking University [3]Faraday Technology China Corp.

出　　处：《Science China(Information Sciences)》2014年第12期172-179,共8页中国科学（信息科学）（英文版）

基　　金：supported by National 02 Key Special Program(Grant No.2009ZX02305-005);National Hightech R&D Program of China(863 Program)(Grant No.2013AA014102);National No.2 Special Key ProjectProgram(Grant No.2012ZX02503005)

摘　　要：A new low-power, area efficiency all-digital delay-locked loop （ADDLL） circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz （DDR3- 667/800/1066/1600） by using Phase Detector （PD）, Delay Control Delay Line （DCDL）, Digital Loop Filter Controller （DLFC） and Delay Generator （DG）. To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A split- control thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps- 1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm2.A new low-power, area efficiency all-digital delay-locked loop （ADDLL） circuit is proposed for DDR3 application. The ADDLL can process the input clock frequency ranging from 333 MHz to 800 MHz （DDR3- 667/800/1066/1600） by using Phase Detector （PD）, Delay Control Delay Line （DCDL）, Digital Loop Filter Controller （DLFC） and Delay Generator （DG）. To achieve 1.6 Gb/s/pin operation, a novel DCDL scheme is employed. The DCDL has a small delay with a shunt capacitor based digitally controlled delay element. A split- control thermometer-code generator generates the control voltages used to set a current in the current-starved inverters. The testchip fabricated with a 40-nm CMOS process gives the ADDLL data rate of 667 Mbps- 1.6 Gbps. Experimental results that show the power consumption is 1.87 mW at 1.1 V with active area is 0.0137 mm2.

关 键 词：all-digital delay-locked loop double-data-rate digitally controlled delay line shunt capacitor thermometer code 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]