Enhanced Total Ionizing Dose Hardness of Deep Sub-Micron Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors by Applying Larger Back-Gate Voltage Stress  

作　　者：郑齐文 崔江维 余学峰 郭旗 周航 任迪远 

机构地区：[1]Key Laboratory of Functional Materials and Devices for Special Environments, Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, Urumqi 830011 [2]Xinjiang Key Laboratory of Electronic Information Material and Device, Urumqi 830011 [3]University of Chinese Academy of Sciences, Beijing 100049

出　　处：《Chinese Physics Letters》2014年第12期82-84,共3页中国物理快报（英文版）

摘　　要：Owing to the fifll isolation and minimization of the silicon active volume, silicon-on-insulator （SOI） tech- nology has better resistance against transient ionizing effects like single event effects （SEE） or latch up.However, the total ionizing dose （TID） irradiation responses of SOI transistors are more complex than bulk-silicon devices. In addition to the gate and par- asitic field leakage current, which are common to SOI and bulk-silicon devices, irradiation induced charges trapped in the SOI buried oxide （BOX） can also affect SOI device performance. Typically, there is a par- asitic edge transistor in the back-gate of SOI devices paralleled with the main transistor, which is formed by the corner region of the silicon island. Due to the high electric field induced by the back-gate voltage at the corner of the silicon island, the threshold of the parasitic edge transistor is lower than the main transistor, resulting in a sub-threshold hump in the transfer characteristic of the back-gate transistor. Even though the threshold of the parasitic edge tran- sistor is lower than the main transistor, it is still larger than zero, which has no effect on the front- gate of devices. However, the sub-threshold hump in the back-gate is the ＇Achilles heel＇ for total dose responses of deep sub-micron SOI n-type metal-oxide- semiconductor field-effect transistors （MOSFETs） iso- lated by shallow trench isolation （STI）. As reported in Refs., the threshold of the parasitic edge transis- tor is negative shifted by radiation-induced charges trapped in STI, leading to off-state leakage in the front-gate of devices.Owing to the fifll isolation and minimization of the silicon active volume, silicon-on-insulator （SOI） tech- nology has better resistance against transient ionizing effects like single event effects （SEE） or latch up.However, the total ionizing dose （TID） irradiation responses of SOI transistors are more complex than bulk-silicon devices. In addition to the gate and par- asitic field leakage current, which are common to SOI and bulk-silicon devices, irradiation induced charges trapped in the SOI buried oxide （BOX） can also affect SOI device performance. Typically, there is a par- asitic edge transistor in the back-gate of SOI devices paralleled with the main transistor, which is formed by the corner region of the silicon island. Due to the high electric field induced by the back-gate voltage at the corner of the silicon island, the threshold of the parasitic edge transistor is lower than the main transistor, resulting in a sub-threshold hump in the transfer characteristic of the back-gate transistor. Even though the threshold of the parasitic edge tran- sistor is lower than the main transistor, it is still larger than zero, which has no effect on the front- gate of devices. However, the sub-threshold hump in the back-gate is the ＇Achilles heel＇ for total dose responses of deep sub-micron SOI n-type metal-oxide- semiconductor field-effect transistors （MOSFETs） iso- lated by shallow trench isolation （STI）. As reported in Refs., the threshold of the parasitic edge transis- tor is negative shifted by radiation-induced charges trapped in STI, leading to off-state leakage in the front-gate of devices.

分 类 号：TN25[电子电信—物理电子学] TP332[自动化与计算机技术—计算机系统结构]