The Impact of Shallow-Trench-Isolation Mechanical Stress on the Hysteresis Effect of Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effects  

作　　者：罗杰馨 陈静 柴展 吕凯 可伟伟 杨燕 王曦 

机构地区：[1]State Key Laboratory of Functional Materials for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050 [2]Graduate University of Chinese Academy of Sciences, Beijing 100049 [3]Departments of Physics, Soochow University, Suzhou 215006

出　　处：《Chinese Physics Letters》2014年第12期89-91,共3页中国物理快报（英文版）

摘　　要：Silicon-on-insulator （SOI） technology is attracting a great deal of attention for applications in very large scale integrated circuits due to their excellent proper- ties such as reduced capacitance, higher drive current and latch-up immunity. The hysteresis effect on the output characteristics could also be important for some special analogous applications reported by Chen et al. The isolation in high density integrated circuits has become very fine to reduce the device size to be- low the sub-0.2 μm regime. For shallow trench isola- tion （STI）, the abrupt transient edge region and the stress between the channel and the isolation region have an undesirable influence on the electrical perfor- mance and reliability. Mechanical stress in the de- vice affects many device characteristics, for example, carrier mobility and hot carrier immunity, and doping diffusion. It is shown for the first time that anoma- lous degradation in time-dependent dielectric break- down （TDDB） for downsized MOSFETs is caused by the compressive stress by STi. An STI-induced en- hanced hot carrier （HC） or negative bias temperature instability （NBTI） effect degradation in p-type MOS- FETs for ultrathin gate oxide devices has been ob- served in Ref. The behavior of the STI disloca- tions and the effect on the junction leakage character- istics during the fabrication of dynamic random access memory （DRAM） with 0.15m technology have been reported in Ref. . In this work, we investigate the influence of STI mechanical stress on the hysteresis effect of PD SOI NMOS devices.Silicon-on-insulator （SOI） technology is attracting a great deal of attention for applications in very large scale integrated circuits due to their excellent proper- ties such as reduced capacitance, higher drive current and latch-up immunity. The hysteresis effect on the output characteristics could also be important for some special analogous applications reported by Chen et al. The isolation in high density integrated circuits has become very fine to reduce the device size to be- low the sub-0.2 μm regime. For shallow trench isola- tion （STI）, the abrupt transient edge region and the stress between the channel and the isolation region have an undesirable influence on the electrical perfor- mance and reliability. Mechanical stress in the de- vice affects many device characteristics, for example, carrier mobility and hot carrier immunity, and doping diffusion. It is shown for the first time that anoma- lous degradation in time-dependent dielectric break- down （TDDB） for downsized MOSFETs is caused by the compressive stress by STi. An STI-induced en- hanced hot carrier （HC） or negative bias temperature instability （NBTI） effect degradation in p-type MOS- FETs for ultrathin gate oxide devices has been ob- served in Ref. The behavior of the STI disloca- tions and the effect on the junction leakage character- istics during the fabrication of dynamic random access memory （DRAM） with 0.15m technology have been reported in Ref. . In this work, we investigate the influence of STI mechanical stress on the hysteresis effect of PD SOI NMOS devices.

分 类 号：TN304.21[电子电信—物理电子学] TQ172.622[化学工程—水泥工业]