高电源电压抑制、低功耗片上低压差线性稳压器的研究与设计  

Research and Design of High PSR,Low power,Chip-level LDO

作　　者：金禹铮 付宇卓[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《微电子学与计算机》2014年第5期163-166,共4页Microelectronics & Computer

摘　　要：为了能更适合于片上集成,在提供稳定电压的同时降低输入电压的噪声,设计了一种新型片上CMOS低压差线性稳压器(LDO),其显著特点是静态电流很小,在3.3V供电电压下,只有10μA的静态电流,功耗很小,适合于片上低功耗集成使用.同时,对LDO的电源电压抑制(PSR)进行了改进,提出了一种有效地使PSR提高的方法,使PSR低频下达到了大约-45dB,最差的情况也能达到-20dB左右,对输入电源的纹波噪声有比较好的抑制作用,更加适合于对噪声敏感的电路集成.In order to reduce the input voltage noise while supplying a stable output voltage and integrate on-chip ,a kind of new CMOS ,chip-level LDO is proposed in this paper .One of the most notable features is that its quiescent current is quite low .With the 3 .3 V power supply ,the quiescent current is only 10 μA .So the power consumption is considerable for chip-level .Meanwhile ,the power supply rejection （PSR） is also promoted with an effective PSR improved method ,which can reach -45 dB in low frequency and the worst case can also reach around -20 dB .So it can better reject the power supply noise at the output and is suitable for noise-sensitive circuits .

关 键 词：LDO线性稳压器 低功耗 高电源电压抑制(PSR) 

分 类 号：TN47[电子电信—微电子学与固体电子学]