高性能差错控制编码的硬件设计与实现  

Hardware Design and Implementation of High-performance Error Control Coding

作　　者：李其虎[1] 孙浩[2] 文运丰[1] 韩伟[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,石家庄050081 [2]国家无线电监测中心,北京100037

出　　处：《半导体光电》2014年第4期673-676,681,共5页Semiconductor Optoelectronics

基　　金：河北省高层次人才项目(B2013003019)

摘　　要：为提高航天测控通信系统中数据传输的可靠性、确保终端接收数据的正确性,需对被传输的测控数据进行高速差错编码。基于循环冗余校验编码,在硬件电路中设计并实现了一种简单高效的差错编码方式。首先将被传输的数据按照一定字节进行分帧,每帧数据加入特定的帧头,每帧数据按字节进行八比特差错编码,差错编码按照查表方式进行。对每帧数据的差错编码值再进行一比特纠错编码。实验仿真结果表明所设计的差错编码具有性能高、硬件资源消耗低和编码速度快等特点,适合于高速大容量数据可靠性传输。In order to improve the reliability of data transmitting and ensure the accuracy of data received at the terminal in space tracking and control system,the data to be transmitted should be encoded with redundancy.Based on the cyclic redundancy coding,a novel effective error control coding algorithm is designed and implemented in the hardware circuit.Firstly,the data are separated to frames with specific header data.Then,data in each frame are encoded according to the 8-bit byte error coding method;also table look-up method is used to process error coding.Thirdly,an extra encoding will be performed for the error coding data.Simulation results illustrate this algorithm works with high performance,low consumption of hardware resources and faster coding speed,which means this algorithm,is suitable for high-speed and large-capacity data transmission.

关 键 词：差错控制 循环冗余编码 纠错编码 FPGA 

分 类 号：TN919.8[电子电信—通信与信息系统]