Performance-driven assignment and mapping for reliable networks-on-chips  

作　　者：Qian-qi LE Guo-wu YANG William N.N.HUNG Xiao-yu SONG Fu-you FAN 

机构地区：[1]School of Computer Science and Engineering, University of Electronic Science and Technology of China [2]Department of Information and Computing Science, Chengdu University of Technology [3]Synopsys Inc., Mountain View, CA 94040, USA [4]Department of Electronic and Computer Engineering, Portland State University, Portland, OR 97207-0751, USA

出　　处：《Journal of Zhejiang University-Science C(Computers and Electronics)》2014年第11期1009-1020,共12页浙江大学学报C辑（计算机与电子（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.60973016 and 61272175);the National Basic Research Program(973) of China(No.2010CB328004);the Youth Backbone Teacher Foundation of Chengdu University of Technology(No.JXGG201305);the Bagui Scholarship Project,China

摘　　要：Network-on-chip(NoC) communication architectures present promising solutions for scalable communication requests in large system-on-chip(SoC) designs. Intellectual property(IP) core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the drawbacks of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite(E3S). Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.Network-on-chip （NoC） communication architectures present promising solutions for scalable communication requests in large system-on-chip （SoC） designs. Intellectual property （IP） core assignment and mapping are two key steps in NoC design, significantly affecting the quality of NoC systems. Both are NP-hard problems, so it is necessary to apply intelligent algorithms. In this paper, we propose improved intelligent algorithms for NoC assignment and mapping to overcome the draw-backs of traditional intelligent algorithms. The aim of our proposed algorithms is to minimize power consumption, time, area, and load balance. This work involves multiple conflicting objectives, so we combine multiple objective optimization with intelligent algorithms. In addition, we design a fault-tolerant routing algorithm and take account of reliability using comprehensive performance indices. The proposed algorithms were implemented on embedded system synthesis benchmarks suite （E3S）. Experimental results show the improved algorithms achieve good performance in NoC designs, with high reliability.

关 键 词：Network-on-chip （NoC） MAPPING ASSIGNMENT Reliability 

分 类 号：TN47[电子电信—微电子学与固体电子学]