通用SPWM发生器的实现及脉冲竞争消除新方法  

Implementation of universal SPWM pulse generator and novel method for pulse competition elimination

作　　者：王跃[1] 杨昆[1] 杨华 陈国柱[1] 

机构地区：[1]浙江大学电气工程学院,浙江杭州310027 [2]圣航科技股份有限公司,浙江湖州313200

出　　处：《浙江大学学报（工学版）》2014年第11期2087-2093,共7页Journal of Zhejiang University：Engineering Science

基　　金：国家自然科学基金资助项目(51177147);浙江省重点科技创新团队资助项目(2010R50021)

摘　　要：为实现载波移相(CPS)正弦脉冲宽度调制(SPWM)策略在级联配电网静止同步补偿器(DSTATCOM)中的应用,设计基于现场可编程门阵列(FPGA)芯片的载波移相通用多路SPWM发生器,载波频率、级联数可通过上位机进行选择.介绍通用多路SPWM发生器的设计原理、硬件结构及其通用性设计方法.针对大功率级联多电平逆变器较低器件开关频率时SPWM调制存在的脉冲竞争现象,分析产生机理并采用在三角波的升、降半周期内限制PWM信号翻转次数的新方法予以消除.在10kV/2MVar的DSTATCOM装置上进行验证实验,实验结果证明所设计SPWM发生器准确、可靠以及脉冲竞争消除新方法的优越性.To implement dual-frequency carrier phase-shifted sinusoidal pulse width modulation （CPS-SP- WM） strategy in cascaded distribution static synchronous compensator （DSTATCOM） system, a field programmable gate array （FPGA） based universal CPS SPWM pulse generator was designed, for which switching frequency as well as cascade number can be selected with master computer. Basic principles, hardware configuration and universality design of the SPWM pulse generator were described. Aimed at un- desired logic competition caused by low switching frequeney in cascaded multi-level converter, the paper analysed its generation mechanism and presented a new method for eliminating the competition pulses hy limiting the PWM reversion times in each rising/descending half cycle of the triangular carrier wave. At last, the SPWM pulse generator was applied to a 10kV/2MVar rated DSTATCOM system, experimental results showed the aecuracy and reliability of the pulse generator, verified the superiority of the proposed eliminating method for the competition pulses.

关 键 词：载波移相SPWM 级联DSTATCOM 现场可编程门阵列芯片(FPGA) SPWM发生器 脉冲竞争 

分 类 号：TM762[电气工程—电力系统及自动化]